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DATA SHEET
SAA7356HL 1394 SBP-2 link layer controller
Preliminary specification File under Integrated Circuits, IC01 2000 Nov 17
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.5 7.6 8 8.1 8.2 8.3 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PIN CONFIGURATION FUNCTIONAL DESCRIPTION Overview SBP-2 automation engine DMA interface Microcontroller interface Intel 8031 interface support Hitachi H8 interface NEC V851 interface support Interrupt handling Address map for the SAA7356HL MICROCONTROLLER COMMUNICATION WITH THE SAA7356HL Communications initiated by the microcontroller Communications initiated by the SAA7356HL Interrupt registers 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 9 10 8.4 8.4.1 8.4.2
SAA7356HL
RAM access for parameter passing Register Access Register definitions for the register access method LIMITING VALUES RECOMMENDED OPERATING CONDITIONS DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
1 FEATURES 2 GENERAL DESCRIPTION
SAA7356HL
* Institute of Electrical and Electronics Engineers (IEEE) 1394-1995 standard link layer controller * Compatible with the P1394a standard * Fully automated Serial Bus Protocol 2 (SBP-2) transaction layer for data storage applications * Interface to many of the industry standard Direct Memory Access (DMA) protocols * Interface to any IEEE1394-1995 or P1394a PHY layer interface * Very low power comma mode * Small package * Single 3.3 V supply voltage with 5 V tolerance. 3 QUICK REFERENCE DATA SYMBOL VDD IDD SCLK 4 PARAMETER supply voltage supply current system clock VDD = 3.3 V
The SAA7356HL is an IEEE1394-1995 and P1394a compliant link layer controller featuring an embedded SBP-2 transaction layer for data storage applications. The SAA7356HL provides full automation of the SBP-2 transaction layer to an extent that the user need not have knowledge of SBP-2 or 1394.
CONDITIONS -
MIN. 3.0 49.147
TYP. 3.3 29 49.152 -
MAX. 3.6 49.157
UNIT V mA MHz
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME LQFP80 DESCRIPTION plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm VERSION SOT315-1
SAA7356HL
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
5 BLOCK DIAGRAM
SAA7356HL
handbook, full pagewidth
SRAM
32-bit data bus LINK CORE
ARBITER SRAM CONTROLLER Req/Ack
1394 PHY interface
flow control
DMA CONTROL
DMA interface
ARBITER
SAA7356HL
MICROCONTROLLER INTERFACE
SBP-2 AUTOMATION ENGINE
GSA038
microcontroller interface
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
6 PIN CONFIGURATION SYMBOL MICRO_ADDR[0] MICRO_ADDR[1] MICRO_ADDR[2] MICRO_ADDR[3] VDD1(P) VSS1(P) MICRO_ADDR[4] MICRO_ADDR[5] MICRO_ADDR[6] MICRO_ADDR[7] VDD2(P) VSS2(P) DMA_DATA[15] DMA_DATA[14] DMA_DATA[13] DMA_DATA[12] DMA_DATA[11] DMA_DATA[10] VDD1(C) VSS1(C) DMA_DATA[9] DMA_DATA[8] DMA_DATA[7] DMA_DATA[6] DMA_DATA[5] DMA_DATA[4] DMA_DATA[3] DMA_DATA[2] VSS3(P) VDD3(P) DMA_DATA[1] DMA_DATA[0] DMA_REQ DMA_ACK VSS2(C) VDD2(C) DMA_READ PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 TYPE(1) I I I I S S I I I I S S I /O I /O I /O I /O I /O I /O S S I /O I /O I /O I /O I /O I /O I /O I /O S S I /O I /O O I S S I /O DESCRIPTION microcontroller address input (bit 0); note 2 microcontroller address input (bit 1); note 2 microcontroller address input (bit 2); note 2 microcontroller address input (bit 3); note 2 supply voltage 1 for periphery ground 1 for periphery microcontroller address input (bit 4); note 2 microcontroller address input (bit 5); note 2 microcontroller address input (bit 6); note 2 microcontroller address input (bit 7); note 2 supply voltage 2 for periphery ground 2 for periphery DMA data input/output (bit 15); note 3 DMA data input/output (bit 14); note 3 DMA data input/output (bit 13); note 3 DMA data input/output (bit 12); note 3 DMA data input/output (bit 11); note 3 DMA data input/output (bit 10); note 3 supply voltage 1 for core ground 1 for core DMA data input/output (bit 9); note 3 DMA data input/output (bit 8); note 3 DMA data input/output (bit 7); note 3 DMA data input/output (bit 6); note 3 DMA data input/output (bit 5); note 3 DMA data input/output (bit 4); note 3 DMA data input/output (bit 3); note 3 DMA data input/output (bit 2); note 3 ground 3 for periphery supply voltage 3 for periphery DMA data input/output (bit 1); note 3 DMA data input/output (bit 0); note 3
SAA7356HL
DMA request signal output in slave mode (acknowledge in master/ATA mode) (may be configured for active HIGH or active LOW) DMA acknowledge signal input in slave mode (request in master/ATA mode) (may be configured for active HIGH or active LOW) ground 2 for core supply voltage 2 for core DMA read strobe input/output (may be configured for active HIGH or active LOW)
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
SYMBOL DMA_WRITE PHY_CTRL[1] PHY_CTRL[0] PHY_DATA[0] PHY_DATA[1] PHY_DATA[2] PHY_DATA[3] VSS4(P) VDD4(P) PHY_DATA[4] PHY_DATA[5] PHY_DATA[6] PHY_DATA[7] VDD5(P) VSS5(P) PHY_SCLK MICRO_SEL[0] PHY_LREQ PHY_ISO MICRO_SEL[1] 1394_MODE RESET TC BT MICRO_CS VDD3(C) VSS3(C) MICRO_INT MICRO_WRITE MICRO_READ MICRO_ALE VSS6(P) VDD6(P) MICRO_DATA[0] MICRO_DATA[1] MICRO_DATA[2] MICRO_DATA[3] 2000 Nov 17
PIN 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
TYPE(1) I /O I /O I /O I /O I /O I /O I /O S S I /O I /O I /O I /O S S I I O I I I /O I - - I S S O I I I S S I /O I /O I /O I /O
DESCRIPTION DMA write strobe input/output (may be configured for active HIGH or active LOW) PHY control line input/output (1); note 4 PHY control line input/output (0); note 4 PHY data input/output (bit 0); notes 4, 5 and 6 PHY data input/output (bit 1); notes 4 and 5 PHY data input/output (bit 2); notes 4 and 5 PHY data input/output (bit 3); notes 4 and 5 ground 4 for periphery supply voltage 4 for periphery PHY data input/output (bit 4); notes 4 and 5 PHY data input/output (bit 5); notes 4 and 5 PHY data input/output (bit 6); notes 4 and 5 PHY data input/output (bit 7); notes 4 and 5 supply voltage 5 for periphery ground 5 for periphery PHY system clock input (49.152 MHz) microcontroller select (0) input; selects microcontroller interface; note 10 PHY-Link request output (used to request arbitration or read/write PHY registers); note 4 PHY isolation barrier input (active LOW). Negated HIGH when the Link and PHY are directly connected or when bus-holder isolation is used; note 4 microcontroller select (1) input; selects microcontroller interface; note 10 note 7 asynchronous master reset input to the SAA7356HL (active LOW) reserved for factory testing; for normal operation should be connected to ground reserved for factory testing; for normal operation should be connected to ground microcontroller chip select input (active LOW) supply voltage 3 for core ground 3 for core microcontroller interrupt open-drain output (active LOW) microcontroller write strobe input (active LOW) microcontroller read strobe input (active LOW) microcontroller address latch enable input; note 8 ground 6 for periphery supply voltage 6 for periphery microcontroller data input/output [bit 0); note 9 microcontroller data input/output (bit 1); note 9 microcontroller data input/output (bit 2); note 9 microcontroller data input/output (bit 3); note 9 6
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
SYMBOL MICRO_DATA[4] MICRO_DATA[5] VSS4(C) VDD4(C) MICRO_DATA[6] MICRO_DATA[7] Notes
PIN 75 76 77 78 79 80
TYPE(1) I /O I /O S S I /O I /O
DESCRIPTION microcontroller data input/output (bit 4); note 9 microcontroller data input/output (bit 5); note 9 ground 4 for core supply voltage 4 for core microcontroller data input/output (bit 6); note 9 microcontroller data input/output (bit 7); note 9
1. Pin type abbreviations: I = Input, O = Output and S = Supply. 2. Used in NEC V851 and 16-bit Intel 8031 microcontroller interface configurations. 3. DMA data to the external buffer manager may be configured for 16 or 8 bits wide. For 16-bit operation pins DMA_DATA[15:0] are used, and for 8-bit operation, pins DMA_DATA[7:0] are used. 4. For more information see IEEE1394-1995 standard, Annex J. 5. Data is expected on PHY_DATA[0:1] for 100 Mbits/s, PHY_DATA[0:3] for 200 Mbits/s and PHY_DATA[0:7] for 400 Mbits/s. 6. To preserve compatibility to the specified Link-PHY interface of the IEEE1394-1995 standard, Annex J, bit 0 is the most significant bit. 7. During Power-on reset, this line is sampled to select between IEEE1394-1995 mode (HIGH) and P1394a mode (LOW). A 22 k pull-up or pull-down resistor should be connected accordingly. This line acts as the MICRO_WAIT line when the V851 microcontroller interface mode is selected. 8. Used in NEC V851 and Intel 8031 (8-bit and 16-bit) microcontroller interface configurations. 9. This is the data bus for all microcontroller interface configurations. This forms the lower address bus for the NEC V851 and Intel 8031 microcontroller configurations. 10. MICRO_SEL [1:0] = `00' selects 8-bit 8031 mode; MICRO_SEL [1:0] = `01' selects H8 mode; MICRO_SEL [1:0] = `10' selects 16-bit 8031 mode; MICRO_SEL [1:0] = `11' V851 mode.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
80 MICRO_DATA[7]
79 MICRO_DATA[6]
76 MICRO_DATA[5]
75 MICRO_DATA[4]
74 MICRO_DATA[3]
73 MICRO_DATA[2]
72 MICRO_DATA[1]
71 MICRO_DATA[0]
66 MICRO_WRITE
handbook, full pagewidth
67 MICRO_READ
68 MICRO_ALE
65 MICRO_INT
62 MICRO_CS
78 VDD4(C)
63 VDD3(C)
70 VDD6(P)
77 VSS4(C)
64 VSS3(C)
69 VSS6(P)
MICRO_ADDR[0] MICRO_ADDR[1] MICRO_ADDR[2] MICRO_ADDR[3] VDD1(P) VSS1(P) MICRO_ADDR[4] MICRO_ADDR[5] MICRO_ADDR[6]
61 BT
1 2 3 4 5 6 7 8 9
60 TC 59 RESET 58 1394_MODE 57 MICRO_SEL[1] 56 PHY_ISO 55 PHY_LREQ 54 MICRO_SEL[0] 53 PHY_SCLK 52 VSS5(P)
MICRO_ADDR[7] 10
SAA7356HL
VDD2(P) 11 VSS2(P) 12 DMA_DATA[15] 13 DMA_DATA[14] 14 DMA_DATA[13] 15 DMA_DATA[12] 16 DMA_DATA[11] 17 DMA_DATA[10] 18 VDD1(C) 19 VSS1(C) 20
DMA_DATA[9] 21 DMA_DATA[8] 22 DMA_DATA[7] 23 DMA_DATA[6] 24 DMA_DATA[5] 25 DMA_DATA[4] 26 DMA_DATA[3] 27 DMA_DATA[2] 28 VSS3(P) 29 VDD3(P) 30 DMA_DATA[1] 31 DMA_DATA[0] 32 DMA_REQ 33 DMA_ACK 34 VSS2(C) 35 VDD2(C) 36 DMA_READ 37 DMA_WRITE 38 PHY_CTRL[1] 39 PHY_CTRL[0] 40
51 VDD5(P) 50 PHY_DATA[7] 49 PHY_DATA[6] 48 PHY_DATA[5] 47 PHY_DATA[4] 46 VDD4(P) 45 VSS4(P) 44 PHY_DATA[3] 43 PHY_DATA[2] 42 PHY_DATA[1] 41 PHY_DATA[0]
GSA017
Fig.2 Pin configuration.
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Preliminary specification
1394 SBP-2 link layer controller
7 7.1 FUNCTIONAL DESCRIPTION Overview
SAA7356HL
The SBP-2 link also provides an interface to an external microcontroller. The microcontrollers supported include 8/16-bit addressing from the Intel 8031 derivatives, the Hitachi H8 and the NEC V851. Through this interface, the microcontroller retrieves the 12-byte Command Descriptor Blocks (CDBs) and provides the command status indication; unsolicited status information is also supported.
The SAA7356HL is an IEEE1394-1995 and P1394a compliant link layer controller. It provides a direct interface between a 1394 bus and a DMA interface found on many buffer managers (see Fig.3). Through this interface, the SBP-2 automation engine performs all transaction layer specific operations; these include the management agent, fetch agent, and page table handling features.
handbook, full pagewidth
MICRO_ADDR [7:0] MICRO_DATA [7:0] MICRO_SEL [1:0] MICRO_ALE PHY_DATA [0:7] PHY_CTRL [0:1] PHY_LREQ PHY_ISO 1394 PHY interface
microcontroller interface
MICRO_READ MICRO_WRITE MICRO_CS 1349-MODE (1) MICRO_INT DMA_DATA [15:0] DMA_REQ
SAA7356HL
IEEE1394/P1394a SBP-2 LINK LAYER CONTROLLER
PHY_SCLK
VDD VSS RESET
DMA interface
DMA_ACK DMA_READ DMA_WRITE
GSA039
(1) Acts as the MICRO_WAIT line when the V851 microcontroller interface mode is selected.
Fig.3 Functional diagram.
7.2
SBP-2 automation engine
The complete SBP-2 transaction layer is supported by the SAA7356HL. This includes the log-in, log-out and reconnect functions in the management agent plus the fetch engine for retrieving linked lists of Operation Request Blocks (ORBs) from the logged-in node. The data transfers plus the required flow control and target node page-table management are also supported. The transaction layer parses the ORBs to extract the CDBs and presents them to the microcontroller. The microcontroller returns status indication to the transaction layer: the SBP-2 engine then returns this information plus the transaction status information to the logged-in node. The SAA7356HL will present all Configuration-ROM reads to the microcontroller. 2000 Nov 17 9
The microcontroller will return the requested information. The SAA7356HL will then add the required header for the 1394 transaction to service these requests. 7.3 DMA interface
The SAA7356HL supports many formats of DMA interface. The DMA bus width may be 8 or 16 bits wide. The polarity of the request, acknowledge, read and write strobes can be configured for active HIGH or active LOW. The DMA controller may also be configured as a master or a slave. In the slave mode, the burst length can also be configured. All configuration details are loaded into the SAA7356HL via a shared page in the Static Random Access Memory (SRAM).
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
In slave mode a buffer data transfer begins when the DMA interface asserts the DMA_REQ pin. The buffer manager responds with the DMA_ACK signal. The burst configuration defines the number of bytes/words to keep DMA_REQ asserted. The settings include: * DMA_REQ is asserted until the last byte/word is transferred or until there is no space/data available in the FIFO * DMA_REQ is asserted and negated for each byte/word transferred * DMA_REQ is not asserted unless there is space/data available in the FIFO * the DMA interface waits until there are at least two bytes/words of data/space in the FIFO before asserting DMA_REQ (in this case, DMA_REQ remains asserted for the two bus transfers and then de-asserts); and * the DMA interface waits until there are at least four bytes/words of data/space in the FIFO before asserting DMA_REQ (in this case, DMA_REQ remains asserted for the four bus transfers and then de-asserts). This process repeats until all of the data is transferred. In slave mode, there are three modes of operation for moving data between the SAA7356HL and the DMA interface: * Mode 0: DMA_WRITE strobes the data from the buffer memory data bus into the FIFO; DMA_READ gates the data from the FIFO onto the buffer memory data bus * Mode 1: DMA_WRITE strobes the data from the buffer memory into the FIFO. DMA_ACK gates data from the FIFO onto the buffer memory data bus * Mode 2: DMA_ACK strobes the data from the buffer memory bus into the FIFO and also gates the data from the FIFO onto the buffer memory data bus. In slave mode the DMA interface drives the DMA_REQ pin and waits for the buffer manager to acknowledge the request via DMA_ACK as described above. In master mode, the buffer manager drives the DMA_REQ pin and the DMA interface acknowledges the availability of data/space with the DMA_ACK pin. The read or write strobes are driven by the buffer manager in slave mode, and by the DMA interface in master mode. All mode selections listed above are also valid in master mode, however it should be noted that the burst configuration is not applicable in master mode. Burst size in master mode is determined by the buffer manager request signal, and DMA interface flow control by the time duration between successive acknowledge assertions or read/write assertions.
SAA7356HL
In master mode the SAA7356HL appears to be an Advanced Technology Attachment (ATA) host and can be connected to an ATA or Advanced Technology Attachment Packet Interface (ATAPI) peripheral. The SAA7356HL output signal (DMA_REQ) behaves like the acknowledge on the Integrated Drive Electronics (IDE) bus; the input signal (DMA_ACK) behaves like the request line on the IDE bus. The configuration information is provided via a communication page which is shared between the microcontroller and the SAA7356HL. The connections for the various modes are shown in Figs 4 and 5. 7.4 Microcontroller interface
Because of the high-level protocol support, only ten addresses are required. The user should note that all of the internal SAA7356HL registers are still accessible and so the chip-select line should be used to ensure that the SAA7356HL is not accessed accidentally. The behaviour on accessing these other addresses is not specified. When used in V851 and H8 modes, the MICRO_WAIT line is asserted within 4 ns of the MICRO_READ falling edge. For all modes of operation, the data bus is the MICRO_DATA bus. The microcontroller interface can be configured for four modes of operation, namely: * Mode 0: 8-bit addressed Intel 8031 peripheral (multiplexed address/data bus) * Mode 1: 8-bit addressed Hitachi H8 peripheral (non-multiplexed address and data buses) * Mode 2: 16-bit addressed Intel 8031 peripheral (lower address from multiplexed address/data bus) * Mode 3: 16-bit addressed NEC V851 peripheral (acting as an 8-bit peripheral). 7.4.1 INTEL 8031 INTERFACE SUPPORT
The microcontroller interface logic supports the industry standard 8031 style interface. On reading, the MICRO_DATA output is enabled as soon as the MICRO_READ is asserted. Before this happens, the address will have already been decoded and the internal Data Out signal asserted. On writing, the data is loaded from the rising edge of MICRO_WRITE.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
handbook, full pagewidth
DMA_REQ DMA_ACK DMA_WRITE
(data direction ->)
DMA_REQ DMA_ACK DMA_WRITE
(data direction ->)
DMA_REQ DMA_ACK
DMA_READ
(data direction <-)
buffer data 16 or 8-bit BUFFER MANAGER slave mode 0 BUFFER MANAGER
buffer data 16 or 8-bit BUFFER MANAGER
buffer data 16 or 8-bit
SAA7356HL
SAA7356HL
SAA7356HL
GSA040
slave mode 1
slave mode 2
Fig.4 Slave Mode 0, 1 and 2
handbook, full pagewidth
DMA_ACK DMA_REQ DMA_REQ DMA_ACK DMA_WRITE
(data direction ->)
DMA_ACK DMA_REQ DMA_REQ DMA_ACK DMA_WRITE
(data direction ->)
DMA_ACK DMA_REQ DMA_REQ DMA_ACK
DMA_READ
(data direction <-)
buffer data 16 or 8-bit BUFFER MANAGER master mode 0 BUFFER MANAGER
buffer data 16 or 8-bit BUFFER MANAGER
buffer data 16 or 8-bit
SAA7356HL
SAA7356HL
SAA7356HL
GSA041
master mode 1
master mode 2
Fig.5 Master Mode 0, 1 and 2.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
7.4.2 HITACHI H8 INTERFACE
SAA7356HL
The MICRO_WAIT line must be low during the falling edge of the (V851) CLK during state T2: this is the same requirement as the H8. Instead of a MICRO_READ and a MICRO_WRITE signal the V851 uses a R/W and DSTB signal. The address lines are time multiplexed and should be latched using the ASTB signal. 7.5 Interrupt handling
In this mode, the address and data buses are non-multiplexed. The address bus is connected directly to the MICRO_ADDR pins and the data bus is connected directly onto the MICRO_DATA pins. The MICRO_CS pin must be asserted before the assertion of the MICRO_READ pin. The SAA7356HL will stop driving the microcontroller data bus when either the MICRO_CS pin or the MICRO_READ pin are negated. The H8 microcontroller supports wait states. The timing is shown in Fig.6. Note that the MICRO_WAIT pin must be low during the falling edge of the (H8) CLK during state T2. Since the relationship between the SAA7356HL and the H8 clock is unknown the MICRO_WAIT pin is asserted low when the MICRO_READ and the MICRO_CS are asserted. The SAA7356HL will de-assert the MICRO_WAIT line once the data is ready for transfer. 7.4.3 NEC V851 INTERFACE SUPPORT
The SAA7356HL may use interrupts to communicate with the microcontroller. The microcontroller will read from the CmdToMicro register to find the interrupt reason. If parameters are required with the command then this is implied in the command byte.These parameters may then be read from the SAA7356HL RAM using the RAM.Offset and the RAM.Next registers. 7.6 Address map for the SAA7356HL
The address mapping for the 4-bit, 8-bit and 16-bit addressing modes is given in Table 1.
The most important timing information for this microcontroller is given in Fig.7. Table 1 Big-endian register map for the SAA7356HL ADDRESS MNEMONIC 4-BIT 0 1 2 3 4 5 6 7 to B C D E F 9C 9D 9E 9F BC BD BE BF, DC to DF FC FD FE FF 8-BIT 16-BIT FF90 FF91 FF92 FF93 FFB0 FFB1 FFB2 Reserved InterruptEnable reserved enables the InterruptReason to assert the microcontroller interrupt line command byte channel from the microcontroller to the SAA7356HL command byte from the SAA7356HL to the microcontroller used to complete the SAA7356HL initialization sequence allows setting of the flags in the InterruptReason register reserved High-byte of the offset address Low-byte for the offset address RAM access register: forces a post-increment of the RAM.Offset address RAM access register: no modification to the RAM.Offset address COMMENT
InterruptReason provides the interrupt sources CmdFromMicro CmdToMicro Sbp2Start InterruptSet
FFB3, Reserved FFD0 to FFD3 FFF0 FFF1 FFF2 FFF3 RAM.OffsetB RAM.OffsetA RAM.Next RAM.Current
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
handbook, full pagewidth
T1 CLK
T2
Tw
T3
MICRO_ADDR
AS
MICRO_READ
MICRO_DATA(read)
MICRO_WRITE
MICRO_DATA(write)
MICRO_WAIT
GSA042
Fig.6 H8 microcontroller interface timing.
handbook, full pagewidth
T1 CLK
T2
Tw
T3
MICRO_ADDR
MICRO_ALE(ASTB)
MICRO_READ(DSTB)
MICRO_DATA(read)
ADDRESS
DATA
MICRO_READ(R/W)
MICRO_DATA(write)
ADDRESS
DATA
MICRO_WAIT
GSA043
Fig.7 V851 microcontroller interface timing.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
8 MICROCONTROLLER COMMUNICATION WITH THE SAA7356HL
SAA7356HL
This style of communication is used to realize a simple command-driven communication protocol in which the microcontroller sends command bytes to the SAA7356HL. If no parameters are required, there is no need to write to a shared memory location and hence there is no need to write to the RAM Access Offset, Current and Next registers. The CmdFromMicro register definition is given in Table 2. In addition to the CmdFromMicro register, the microcontroller can also write to the Sbp2Start register. This is used in the system initialization sequence. The value that is written has no significance and reading from this address will return zeros. When using this command to initialize the SAA7356HL, the microcontroller may first write to a pre-designated memory area for the parameter passing and then write to the Sbp2Start register to start the requested action. The Sbp2Start register definition is given in Table 3. 8.2 Communications initiated by the SAA7356HL
The communications protocol from a hardware perspective is described in the following sections. The automation engine within the SAA7356HL performs all of the functions necessary to support the SBP-2 protocol layer. The microcontroller and the SAA7356HL communicate via command registers and access to the shared RAM resource. The microcontroller will download the configuration information into the SAA7356HL after a Power-on reset. Once this has been done, the power-on sequence will be completed when the microcontroller writes any value to the Sbp2Start register. To download the configuration information, the microcontroller simply copies a binary image (provided by Philips Semiconductors) and writes repetitively into the RAM.Next address. 8.1 Communications initiated by the microcontroller
The microcontroller may send a message to the SAA7356HL by writing to the CmdFromMicro register. Once the SAA7356HL has used this register, the SAA7356HL will assert the maskable interrupt, InterruptReason.CmdClr, to the microcontroller. The value in the CmdFromMicro register will remain. On receiving the InterruptReason.CmdClr interrupt, the microcontroller will read from the InterruptReason register to determine the source of this interrupt. To clear the interrupt, the microcontroller must write a logic 1 to the InterruptReason.CmdClr bit: writing a logic 0 to this location has no effect. An alternative control protocol may be used. As the SAA7356HL acknowledges the CmdFromMicro, the InterruptReason.CmdClr is asserted as before. The user may decide to mask this interrupt and use a polling technique. On detecting completion of the previous command via InterruptReason.CmdClr, the microcontroller may write another command into the CmdFromMicro register: this will clear the InterruptReason.CmdClr flag and so there is no need for the microcontroller to perform another operation to explicitly clear this flag.
The SAA7356HL has only one form of communication to the microcontroller: the SAA7356HL will write to the CmdToMicro register. On writing to this register, the maskable CmdMicro bit in the InterruptReason register is asserted, which in turn may assert the maskable interrupt to the microcontroller. The microcontroller will read from the InterruptReason register to determine the cause of the interrupt. If no data is required from the communication then the microcontroller can determine this from the value in the CmdToMicro register. The CmdToMicro register definition is given in Table 4. If data or parameters are needed then the SAA7356HL will first write to the RAM and then write to the CmdToMicro register. To signal acknowledgment of the interrupt, the microcontroller writes a logic 1 to the CmdMicro bit in the InterruptReason register which also has the effect of clearing the CmdMicro bit and negating the interrupt (if no other interrupts are pending): writing a logic 0 to the CmdMicro bit has no effect. On signalling the acknowledgment, the value in the CmdToMicro register is unchanged, but now the SAA7356HL is free to modify the CmdToMicro register contents.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
Table 2 CmdFromMicro register definition (read/write) BIT 7 Command(7:0) Sbp2Start register definition (read/write) BIT 7 Command(7:0) CmdToMicro register definition (read/write) BIT 7 Command(7:0) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
SAA7356HL
BYTE NUMBER 0 Table 3
BIT 1
BIT 0
BYTE NUMBER 0 Table 4
BIT 1
BIT 0
BYTE NUMBER 0 8.3
BIT 1
BIT 0
Interrupt registers
As mentioned in the previous section, the communications may be interrupt driven. To facilitate this there is one InterruptReason and one InterruptEnable register. The interrupt to the microcontroller is of the AND-OR type and is asserted when any of the maskable interrupts are enabled and active: to enable an interrupt, the corresponding field in the InterruptEnable register must be set to logic 1. Reading from the InterruptReason register provides the un-masked value: this allows polling if desired. The InterruptEnable and InterruptReason register definitions are shown in Tables 5 and 6 respectively. Table 5 InterruptEnable register definition (read/write) BIT 7 Reserved InterruptReason register definition (read/write) BIT 7 Reserved BIT 6 BIT 5 BIT 6 BIT 5
In addition to these two registers, the microcontroller may set the values in the InterruptReason register: this may be used for setting initial conditions, for example. To set the required bits, a logic 1 must be written to the flag location in the InterruptSet register: writing a logic 0 to any bit-field has no effect. The InterruptSet register definition is given in Table 7. It is recommended that only the InterruptReason.CmdClr flag is set as InterruptReason.CmdMicro will cause a maskable interrupt to be asserted to the microcontroller. The definition of the InterruptReason, InterruptEnable and the InterruptSet register fields are shown in Table 8.
BYTE NUMBER 0 Table 6
BIT 4
BIT 3
BIT 2 CmdMicro
BIT 1 BusReset
BIT 0 CmdClr
BYTE NUMBER 0 Table 7
BIT 4
BIT 3
BIT 2 CmdMicro
BIT 1 BusReset
BIT 0 CmdClr
InterruptSet register definition (write only, read via InteruptReason) BIT 7 Reserved BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 CmdMicro BIT 1 Reserved BIT 0 CmdClr
BYTE NUMBER 0
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Table 8 Definition of the InterruptReason, InterruptEnable and InterruptSet register fields VALUE 0 1 BusReset CmdMicro Reserved 8.4 0 1 0 1 X default condition: no action occurred COMMENT
SAA7356HL
MNEMONIC CmdClr
the SAA7356HL device has acknowledged the write to the CmdFromMicro register default condition: no action occurred the SAA7356HL has detected a serial bus reset default condition: no action occurred the SAA7356HL has written a command into the CmdToMicro register reserved and set to zero Accesses to the RAM.Current address allow reads and writes to the data in the RAM.Offset location without altering the RAM.Offset address. The ability to write to anywhere within the RAM is used for the power-on sequence. 8.4.2 REGISTER DEFINITIONS FOR THE REGISTER ACCESS
METHOD
RAM access for parameter passing
Within the SAA7356HL there is a 16 kbyte RAM. This is shared between: the IEEE1394 transaction FIFOs, the code for the automation engine and its local storage requirements, and the shared memory area for communications with the microcontroller. The SAA7356HL user must understand how this shared memory is accessed in order to write and read the communications parameters. Each of the read and write accesses to the FIFOs are byte-wide and the offset addresses are byte offsets. 8.4.1 REGISTER ACCESS
This section defines the register structure for the RAM registers. The RAM.Offset registers are used to index into the RAM inside the SAA7356HL. The index is a byte address. The RAM.Offset register definition is shown in Table 9. The RAM.Next register is used to read or write to the RAM location addressed by the RAM.Offset register. Once an access has been made, the value of the RAM.Offset register is incremented to simplify the process of reading or writing contiguous memory areas. The RAM.Next register definition is shown in Table 10. The RAM.Current register is used to read or write to the RAM location addressed by the RAM.Offset register. Once an access has been made there is no change to the RAM.Offset register. The RAM.Current register definition is shown in Table 11.
The RAM can be directly accessed to upload the code into the SAA7356HL. The C-structure for the registers for the RAM access is shown below. struct RAM { U16; offset; // absolute offset into the RAM U8; next; // read/write data at offset and post-increment U8; current; // read/write data at offset }; The RAM.Offset field allows the microcontroller to access anywhere within the SAA7356HL RAM. The RAM.Next accesses will access the RAM.Offset address and post-increment the offset pointer.
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Table 9 Definition of the RAM.Offset registers (read/write) BIT 7 RAM.Offset(7:0) Reserved RAM.Offset (13:8) BIT6 BIT 5 BIT 4 BIT 3 BIT 2
SAA7356HL
BYTE NUMBER 0 1
BIT 1
BIT 0
Table 10 Definition of the RAM.Next register (read/write) BYTE NUMBER 0 BIT 7 RAM.Next(7:0) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Table 11 Definition of the RAM.Current register (read/write) BYTE NUMBER 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RAM.Current(7:0)
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9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to ground (ground = 0 V); notes 1 and 2. SYMBOL VDD IIK VI PARAMETER supply voltage input clamping diode current input voltage microcontroller and DMA pins PHY pins IOK VO IO(source) IO(sink) ISS - ICC Tstg Tamb Ptot output clamping diode current output voltage output source current output sink current VCC or GND current storage temperature ambient temperature total power dissipation package comma mode Notes 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in "Recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 oC. 10 RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VI input voltage PARAMETER supply voltage microcontroller and DMA pins PHY pins VIH VIL IOH IOL tt(i)(r)/V tt(i)f)/V Tamb SCLK ti(r) ti(f) 2000 Nov 17 HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current input transition rise time input transition fall time ambient temperature system clock input rise time input fall time 18 CONDITIONS 0 0 2.0 - - - 0 0 0 49.147 - - MIN. 3.0 MAX. 3.6 5.5 3.6 - 0.8 4 -4 20 20 70 49.157 10 10 V V V V V mA mA ns/V ns/V C MHz ns ns UNIT CONDITIONS - -0.5 - - -0.5 - - - -60 0 - - MIN. -0.5 MAX. +4.0 -50 +5.5 V mA V UNIT
VDD + 0.5 V 50 150 150 150 +150 70 380 82 mA mA mA mA C C mW W VDD + 0.5 V
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
11 DC CHARACTERISTICS SYMBOL VIH VIL VI(th)(r) VI(th)(f) VOH1 VOL1 VOH2 VOL2 IIL IOZ IDD Notes 1. Microcontroller and DMA interface pins. 2. PHY-Link data and control and PHY_SCLK pins. 3. PHY-Link data and control pins. 4. PHY_SCLK pin. 5. Microcontroller, DMA and PHY_LREQ pins. 6. Under idle conditions the average value is 108 mA. PARAMETER HIGH-level input voltage LOW-level input voltage CONDITIONS note 1 note 1 2.4 - MIN. - - TYP. -
SAA7356HL
MAX. 0.8
UNIT V V
input voltage threshold, rising note 2 edge input voltage threshold, falling note 2 edge HIGH-level output voltage 1 LOW-level output voltage 1 HIGH-level output voltage 2 LOW-level output voltage 2 input leakage current 3-state output current active supply current note 1 note 1 note 3 note 3 note 1 note 4 note 5 note 3 VDD = 3.3 V; note 6
0.5VDD + 0.12 - 0.5VDD - 0.66 - 2.4 2.9 - - - - - - - - - - - - - - -
0.5VDD + 0.66 V 0.5VDD - 0.12 V - 0.4 - 0.4 1 100 5 200 - V V V V A A A A mA
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12 AC CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN.
SAA7356HL
TYP. - - - - - - - - - - -
MAX. - 25 25 25 - - - - 10 10 -
UNIT
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 0; see Fig.8 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 cycle time DMA_REQ de-assert from DMA_ACK assert (single word DMA) DMA_REQ de-assert from DMA_WRITE assert (multi-word DMA) DMA_REQ de-assert from DMA_READ assert (multi-word DMA) DMA_REQ assert after DMA_ACK de-assert write data set-up write data hold DMA_WRITE active pulse duration read data stable after DMA_READ active read data 3-state after DMA_READ inactive DMA_REQ assert after DMA_READ and DMA_WRITE negated 67 - - - 8 15 5 25 - 5 68 ns ns ns ns ns ns ns ns ns ns ns
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 1; see Fig.9 t0 t1 t2 t3 t4 t5 t6 t7 t8 t0 t1 t2 t3 t4 t5 t6 t7 cycle time DMA_REQ de-assert from DMA_ACK assert (single word DMA) DMA_REQ de-assert from DMA_WRITE assert (multi-word DMA) DMA_REQ assert after DMA_ACK de-assert read data stable after DMA_ACK assert read data 3-state after DMA_ACK inactive write data set-up write data hold DMA_WRITE active pulse width 67 - - 5 - 5 15 5 25 - - - - - - - - - - - - - - - - - - 25 25 - 10 10 - - - - 25 - - - - 10 10 ns ns ns ns ns ns ns ns ns
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 2; see Fig.10 cycle time DMA_REQ de-assert from DMA_ACK assert (single word DMA) DMA_REQ assert after DMA_ACK de-assert write data set-up write data hold DMA_ACK active pulse duration during data write read data stable after DMA_ACK assert read data 3-state after DMA_ACK de-assert 67 - 5 15 5 25 - 5 ns ns ns ns ns ns ns ns
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SAA7356HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MAX. - 30 30 30 - - - - 15 30 - - 30 30 - 15 30 - - - - - 30 - - - - 15 30
UNIT
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 0; note 1; see Fig.11 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t0 t1 t2 t3 t4 t5 t6 t7 cycle time DMA_REQ de-assert from DMA_ACK assert (single word DMA) DMA_REQ de-assert from DMA_WRITE assert (multi-word DMA) DMA_REQ de-assert from DMA_READ assert (multi-word DMA) DMA_REQ assert after DMA_ACK de-assert write data set-up write data hold DMA_WRITE active pulse duration read data stable after DMA_READ active read data 3-state after DMA_READ inactive DMA_WRITE active pulse duration 40 - - - 0 20 0 20 - 25 20 ns ns ns ns ns ns ns ns ns ns ns
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 1; note 1; see Fig.12 cycle time DMA_REQ de-assert from DMA_ACK assert (single word DMA) DMA_REQ de-assert from DMA_WRITE assert (multi-word DMA) DMA_REQ assert after DMA_ACK de-assert read data stable after DMA_ACK assert read data 3-state after DMA_ACK inactive write data set-up write data hold DMA_WRITE active pulse width DMA_ACK active pulse width 40 - - 0 - 25 20 0 20 20 ns ns ns ns ns ns ns ns ns ns
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 2; note 1; see Fig.13 cycle time DMA_REQ de-assert from DMA_ACK assert (single word DMA) DMA_REQ assert after DMA_ACK de-assert write data set-up write data hold DMA_ACK active pulse duration during data write read data stable after DMA_ACK assert read data 3-state after DMA_ACK de-assert 40 - 0 20 0 20 - 25 ns ns ns ns ns ns ns ns
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SAA7356HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - - - - - - - - - - - - - - - - - - - - - - -
MAX. - - 10 - - - - 280 - - - - 280 30 - - - - - - - - 4 20
UNIT
PHY-LINK INTERFACE TIMING; see Figs 14 and 15 t1 t2 t3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 Notes 1. ATA Multi-word Direct Memory Access (MDMA) protocol with all timing based on an internal DMA interface 50 MHz system clock. 2. MICRO_ALE must pulse to capture a new register address for the Intel 8031 and the NEC V851 modes. 3. t10 must also be satisfied. 4. If MICRO_READ is held LOW, the time from MICRO_CS LOW to stable data is t5 and the data release time from MICRO_CS HIGH is t11. 5. This is larger than the typical read strobe timing. To meet these requirements, either the microcontroller clock will be stopped by the buffer manager device, or the microcontroller must insert its own wait states. 6. t5 must also be satisfied. 7. If MICRO_WRITE is held LOW, data set-up to MICRO_CS HIGH is t15 and data hold from MICRO_CS is t16. 8. t3 minimum = 2 x 3tCP + 5 for successive FIFO reads or a FIFO read or write followed by a read of the FIFO flag registers. 9. This time relates to accesses to addresses other than RAM.Next and RAM.Current. 10. This time relates to accesses to the addresses RAM.Next and RAM.Current. 2000 Nov 17 22 PHY-Link set-up time PHY-Link hold time PHY-Link output delay 6 0 2 ns ns ns
REGISTER INTERFACE TIMING; see Figs 16, 17, 18, 19, 20, 21 and 22 address set-up to MICRO_ALE LOW address hold from MICRO_ALE LOW MICRO_ALE pulse width MICRO_ALE LOW to MICRO_CS LOW MICRO_CS LOW to data valid MICRO_CS HIGH to MICRO_ALE HIGH MICRO_CS set-up to MICRO_READ LOW MICRO_READ pulse width MICRO_READ HIGH to MICRO_CS HIGH MICRO_READ LOW to data valid MICRO_READ HIGH to data bus disable MICRO_CS set-up to MICRO_WRITE LOW MICRO_WRITE pulse width MICRO_WRITE HIGH to MICRO_CS HIGH data set-up to MICRO_WRITE HIGH data hold from MICRO_WRITE HIGH MICRO_WRITE HIGH to MICRO_ALE HIGH MICRO_WRITE HIGH to MICRO_WRITE HIGH MICRO_READ LOW to MICRO_WAIT LOW data valid to MICRO_WAIT HIGH note 8 note 9 note 10 note 7 note 7 note 4 note 5 note 4 note 6 note 3 note 2 10 10 20 10 - 0 0 280 0 - 2 0 30 0 15 4 280 460 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCP + 5 -
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Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
handbook, full pagewidth
t0
DMA_REQ t1 DMA_ACK t2 t7 DMA_WRITE t5 DMA_DATA [15:0] t3 DMA_READ t8 DMA_DATA [15:0] read data
GSA044
t4
t10
t6 write data t10
t9
DMA_REQ is configured active HIGH. DMA_ACK, DMA_WRITE and DMA_READ are configured active LOW.
Fig.8 DMA interface write/read timing diagram for slave mode 0.
handbook, full pagewidth
t0
DMA_REQ t1 DMA_ACK t4 DMA_DATA [15:0] t8 DMA_WRITE t6 DMA_DATA [15:0] write data
GSA045
t3 t2 t5 read data
t7
DMA_REQ is configured active HIGH. DMA_ACK, DMA_WRITE and DMA_READ are configured active LOW.
Fig.9 DMA interface write/read timing diagram for slave mode 1.
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t0
DMA_REQ t1 t5 DMA_ACK t3 DMA_DATA [15:0] t6 DMA_DATA [15:0] read data
GSA046
t2
t4
write data t7
DMA_REQ is configured active HIGH. DMA_ACK is configured active LOW.
Fig.10 DMA interface write/read timing diagram for slave mode 2.
handbook, full pagewidth
t0
DMA_REQ t1 t10 DMA_ACK t2 t7 DMA_WRITE t5 DMA_DATA [15:0] t3 t10 DMA_READ t8 DMA_DATA [15:0] read data
GSA047
t4
t6 write data
t9
DMA_REQ is configured active HIGH. DMA_ACK, DMA_WRITE and DMA_READ are configured active LOW.
Fig.11 DMA interface write/read timing diagram for master mode 0.
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SAA7356HL
handbook, full pagewidth
t0
DMA_REQ t1 t9 t2 DMA_ACK t4 DMA_DATA [15:0] t8 DMA_WRITE t6 DMA_DATA [15:0] write data
GSA048
t3
t5 read data
t7
DMA_REQ is configured active HIGH. DMA_ACK and DMA_WRITE are configured active LOW.
Fig.12 DMA interface write/read timing diagram for master mode 1.
handbook, full pagewidth
t0
DMA_REQ t1 t5 DMA_ACK t3 DMA_DATA [15:0] t6 DMA_DATA [15:0] read data
GSA049
t2
t4
write data t7
DMA_REQ is configured active HIGH. DMA_ACK is configured active LOW.
Fig.13 DMA interface write/read timing diagram for master mode 2.
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SAA7356HL
handbook, full pagewidth
PHY_SCLK t1 PHY_DATA [7:0] PHY_CTRL [1:0]
GSA050
t2
Fig.14 Data and control input set-up and hold timing waveforms.
handbook, full pagewidth
PHY_SCLK t3
PHY_DATA [7:0] PHY_CTRL [1:0] PHY_LREQ
GSA051
Fig.15 Data, control and PHY_LREQ output delay timing waveforms.
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SAA7356HL
handbook, full pagewidth MICRO_ADDR [7:0]
(16-bit mode only) t3 MICRO_ALE
UPPER ADDRESS
UPPER ADDRESS
t4 MICRO_CS t7 MICRO_READ t1 MICRO_DATA [7:0] ADDRESS t2 t10 t5 DATA t8 t9
t6
t11
GSA052
Fig.16 8 or 16-bit addressed 8031 register read timing diagram.
handbook, full pagewidth [7:0] MICRO_ADDR
(16-bit mode only) t3 MICRO_ALE
ADDRESS
ADDRESS
t6 t4 MICRO_CS t12 MICRO_WRITE t18 t1 MICRO_DATA [7:0] ADDRESS t2 t15 t16 DATA ADDRESS DATA
GSA053
t17
t13
t14
Fig.17 8 or 16-bit addressed 8031 register write timing diagram.
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SAA7356HL
handbook, full pagewidth
MICRO_ADDR
ADDRESS t6
MICRO_CS t7 MICRO_READ t10 t5 MICRO_DATA DATA
GSA054
t8
t9
t11
Fig.18 8-bit addressed H8 register read timing diagram.
handbook, full pagewidth
MICRO_ADDR
ADDRESS t6
MICRO_CS t7 MICRO_READ t10 t5 MICRO_DATA t19 MICRO_WAIT t 20
GSA055
t8
t9
t11 DATA
Fig.19 8-bit addressed H8 register read timing diagram with MICRO_WAIT asserted.
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handbook, full pagewidth
MICRO_ADDR
ADDRESS
ADDRESS
MICRO_CS t12 MICRO_WRITE t18 t13 t14
t15 MICRO_DATA
t16 DATA
DATA
GSA056
Fig.20 8-bit addressed H8 register write timing diagram.
handbook, full pagewidth
MICRO_ADDR [7:0]
ADDRESS t3
MICRO_ALE t4 MICRO_CS t7 MICRO_READ t1 MICRO_DATA [7:0] ADDRESS t2 t5 DATA
GSA057
t6
t8
t9
t10
t11
Fig.21 16-bit addressed V851 register read timing diagram.
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SAA7356HL
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MICRO_ADDR [7:0]
ADDRESS t3
ADDRESS
MICRO_ALE t6 t4 MICRO_CS t12 MICRO_WRITE t18 t1 MICRO_DATA [7:0] ADDRESS t2 t15 t16 DATA ADDRESS DATA
GSA058
t17
t13
t14
Fig.22 16-bit addressed V851 register write timing diagram.
13 APPLICATION INFORMATION
handbook, full pagewidth
DRAM
CD-RW ENGINE
I2S-bus BUFFER MANAGER DMA SBP-2 LINK PHY 1394 bus 1394 PHY
GSA059
CD-RW LOADER
SPI
SAA7391
SAA7356HL
MICROCONTROLLER
Fig.23 Application diagram.
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14 PACKAGE OUTLINE LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SAA7356HL
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp 80 1 pin 1 index 20 ZD bp D HD wM B vM B vM A L 21 detail X Lp A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1.0 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-19
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15 SOLDERING 15.1 Introduction to soldering surface mount packages
SAA7356HL
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SAA7356HL
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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16 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
SAA7356HL
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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NOTES
SAA7356HL
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Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 70
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp36
Date of release: 2000
Nov 17
Document order number:
9397 750 06181

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